# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s

--- |
  ; ModuleID = 'massive.ll'
  source_filename = "massive.ll"
  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
  target triple = "thumbv8.1m.main"

  define dso_local arm_aapcscc void @massive(ptr nocapture %a, ptr nocapture readonly %b, ptr nocapture readonly %c, i32 %N) {
  entry:
    %cmp8 = icmp eq i32 %N, 0
    br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader

  for.body.preheader:                               ; preds = %entry
    %scevgep = getelementptr i32, ptr %a, i32 -1
    %scevgep4 = getelementptr i32, ptr %c, i32 -1
    %scevgep8 = getelementptr i32, ptr %b, i32 -1
    %start = call i32 @llvm.start.loop.iterations.i32(i32 %N)
    br label %for.body

  for.cond.cleanup:                                 ; preds = %for.body, %entry
    ret void

  for.body:                                         ; preds = %for.body, %for.body.preheader
    %lsr.iv9 = phi ptr [ %scevgep8, %for.body.preheader ], [ %scevgep10, %for.body ]
    %lsr.iv5 = phi ptr [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ]
    %lsr.iv1 = phi ptr [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ]
    %0 = phi i32 [ %start, %for.body.preheader ], [ %3, %for.body ]
    %size = call i32 @llvm.arm.space(i32 4096, i32 undef)
    %scevgep3 = getelementptr i32, ptr %lsr.iv9, i32 1
    %1 = load i32, ptr %scevgep3, align 4
    %scevgep7 = getelementptr i32, ptr %lsr.iv5, i32 1
    %2 = load i32, ptr %scevgep7, align 4
    %mul = mul nsw i32 %2, %1
    %scevgep11 = getelementptr i32, ptr %lsr.iv1, i32 1
    store i32 %mul, ptr %scevgep11, align 4
    %scevgep2 = getelementptr i32, ptr %lsr.iv1, i32 1
    %scevgep6 = getelementptr i32, ptr %lsr.iv5, i32 1
    %scevgep10 = getelementptr i32, ptr %lsr.iv9, i32 1
    %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
    %4 = icmp ne i32 %3, 0
    br i1 %4, label %for.body, label %for.cond.cleanup
  }

  ; Function Attrs: nounwind
  declare i32 @llvm.arm.space(i32 immarg, i32) #0

  ; Function Attrs: noduplicate nounwind
  declare i32 @llvm.start.loop.iterations.i32(i32) #1

  ; Function Attrs: noduplicate nounwind
  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1

  ; Function Attrs: nounwind
  declare void @llvm.stackprotector(ptr, ptr) #0

  attributes #0 = { nounwind }
  attributes #1 = { noduplicate nounwind }

...
---
name:            massive
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: massive
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 0, 8, implicit-def $itstate
  ; CHECK:   tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
  ; CHECK: bb.1.for.body.preheader:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r3
  ; CHECK:   renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
  ; CHECK:   dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
  ; CHECK: bb.2.for.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2
  ; CHECK:   dead renamable $r3 = SPACE 4096, undef renamable $r0
  ; CHECK:   renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
  ; CHECK:   renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7)
  ; CHECK:   renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14 /* CC::al */, $noreg
  ; CHECK:   early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep11)
  ; CHECK:   renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
  ; CHECK:   t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
  ; CHECK:   tB %bb.3, 14 /* CC::al */, $noreg
  ; CHECK: bb.3.for.cond.cleanup:
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r3, $r7, $lr

    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr
    t2IT 0, 8, implicit-def $itstate
    tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate

  bb.1.for.body.preheader:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2, $r3, $r7, $lr

    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg
    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
    renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg
    $lr = tMOVr $r3, 14, $noreg
    $lr = t2DoLoopStart killed $r3

  bb.2.for.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $r0, $r1, $r2

    dead renamable $r3 = SPACE 4096, undef renamable $r0
    renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load (s32) from %ir.scevgep3)
    renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load (s32) from %ir.scevgep7)
    renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg
    early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store (s32) into %ir.scevgep11)
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14, $noreg

  bb.3.for.cond.cleanup:
    tPOP_RET 14, $noreg, def $r7, def $pc

...
